1. Field of the Invention
The present invention relates to integrated circuit testing. More specifically, the present invention implements a method and apparatus for testing the connectivity of an individual integrated circuit unit to a circuit board.
2. Art Background
In an integrated circuit, electronic circuit elements, such as transistors and resistors, are packed together on a single chip of silicon or other material. Typically, an integrated circuit is designed to perform a specific function. Modern integrated circuits can provide a very sophisticated functionality and therefore can be extremely complex. It is not unusual for an integrated circuit to have hundreds of thousands, or even millions, of circuit elements.
Although an integrated circuit can provide a tremendous amount of functionality, it typically does not operate by itself. Instead, an integrated circuit chip generally functions as a component of a larger system. FIG. 1 depicts a system wherein integrated circuit 100 is coupled to the rest of the system 110. In FIG. 1, input signals 120 are sent to integrated circuit 100 from the rest of the system 110. Similarly, output signals 130 are sent from the integrated circuit 100 to the rest of the system 110. Input 120 and output 130 signals permit integrated circuit 100 to communicate with the rest of the system 110.
Typically, integrated circuit 100 will have pins that are used as conduits to carry input 120 and output 130 signals. Frequently, integrated circuit 100 is coupled to the rest of the system 110 by soldering the pins of integrated circuit 100 into place on a circuit board. When integrated circuit 100 is mounted to a circuit board by soldering, it is possible that one or more of the soldered connections may be defective. Alternately, integrated circuit 100 can be mounted to a circuit board by inserting the pins of integrated circuit 100 into a socket on the circuit board. When inserting integrated circuit 100 into the socket, one or more pins can be bent thereby also causing a defective connection between the circuit board and the integrated circuit 100.
There are basically two types of defective connections. In the first type, an open condition occurs such that there is no electrical connection from a pin of integrated circuit 100 to the board. In the second type of solder defect, a short exists such that two or more pins are connected together electrically. If a connection defect has occurred, integrated circuit 100, and hence the system containing integrated circuit 100, will not function properly. Therefore, it is desirable to have a method to test the connectivity of integrated circuit 100 to the rest of the system 110. Such a test is commonly called a boundary scan test because the pins of integrated circuit 100 form the "boundary" through which integrated circuit 100 interfaces with the rest of the system 110.
One way to perform a traditional boundary scan test on an integrated circuit coupled to a printed circuit board is set forth in a standard established by the Institute of Electrical and Electronics Engineers (IEEE). This standard is referred to as the IEEE standard 1149.1. The IEEE 1149.1 test is well known in the art and is typical of boundary scan tests. A complete description of the IEEE 1149.1 standard and test can be found in the publication: IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronics Engineers, New York, N.Y., 1990. A complete description of the IEEE 1149.1 standard and test can also be found in the publication: The Test Access Port and Boundary-Scan Architecture, by Colin M. Maunder and Rodham E. Tulloss, IEEE Computer Society Press, Los Alimitos, Calif., 1990.
FIG. 2 illustrates an integrated circuit that has a boundary scan test capability. In FIG. 2, core 210 of integrated circuit 200 is a genetic block of logic that provides the core functionality of the integrated circuit. In actuality, an integrated circuit will have scores or even hundreds of pins. For the purposes of this discussion, however, there are basically only three types of pins: input pins, output pins and bi-directional pins. As their names imply, input pins are used to carry input signals to the integrated circuit and output pins are used to carry output signals from the integrated circuit. Bi-directional pins are a hybrid between input and output pins and therefore can carry signals both to and from the integrated circuit. In FIG. 2, integrated circuit 200 has been simplified so that it only has one non-boundary test related pin per type (i.e. input pin 220, output pin 230 and bi-directional pin 250).
Input pin 220 is used to supply an input signal to core 210. Input driver 225 is placed in the path between input pin 220 and core 210 and amplifies the input signal asserted on input pin 220. Similarly, output pin 230 is used to carry an output signal from core 210. Output driver 235 is placed in the path between output pin 230 and core 210 and amplifies the output signal asserted by integrated circuit 200 on output pin 230.
Bi-directional pin 250 is used to supply an input signal to core 210 and to carry an output signal from core 210. Input driver 255 is placed in the path between bi-directional pin 250 and core 210 and amplifies the input signal asserted on bi-directional pin 250. Similarly, output driver 265 is placed in the path between bi-directional pin 250 and core 210 and amplifies the output signal asserted by integrated circuit 200 on bi-directional pin 250. Output drivers 235 and 265 can both be individually tristated.
Test access port control logic 240 is part of integrated circuit 200 and controls the boundary of integrated circuit 200 during a boundary scan test. Test access port control logic 240, in turn, is controlled externally using input signals TEST IN. The results of the boundary scan test are carried out of integrated circuit 200 from test access port control logic 240 by signal TEST OUT. Typically, input signals TEST IN are supplied to integrated circuit 200 over dedicated input test pins. Typically, signal TEST OUT is output from integrated circuit 200 over a dedicated output test pin.
Multiplexers (MUXs) 237 and 267 are controlled by test tristate control 270. Test tristate control 270. in turn, is controlled by access port control logic 240. When integrated circuit 200 is not being tested, multiplexers 237 and 267 are set so that core 210 controls the enabling and disabling (tristating) of output drivers 235 and 265, respectively. During a boundary scan test, test tristate control 270 can set multiplexers 237 and 267 so that test tristate control 270 can control the enabling and disabling of output drivers 235 and 265.
Testing logic 222 is controlled by test access port control logic 240 and resides on the path between input pin 220 and core 210. Although testing logic 222 is shown in FIG. 2 as being placed between input pin 220 and driver 225, this is an implementation issue. In a variation of the prior art, testing logic 222 is placed between driver 225 and core 210.
When integrated circuit 200 is not being tested, testing logic 222 permits an input signal placed on input pin 220 to pass through to core 210. During a test, test access port control logic 240 can control testing logic 222 and thereby sample the value of the digital signal placed on input pin 220. This captured digital value is then sent by test access port control logic 240 back out of integrated circuit 200 over the dedicated test output pin 230. Test access control logic 240 can also cause test logic 222 to capture a digital value sent by test access port control logic 240. Typically, this digital value is sent to integrated circuit 200 over one of the dedicated test input pins. This captured digital value can then be sent to core 210 from testing logic 222. In this way, test access port control logic 240 can override the input signal placed on input pin 220 during a test.
Testing logic 232 is similar to testing logic 222 and is also controlled by test access port control logic 240. Testing logic 232 resides on the path between output pin 230 and core 210. Although testing logic 232 is shown in FIG. 2 as being placed between output pin 230 and driver 235, this is an implementation issue. In an alternate embodiment, testing logic 232 is placed between driver 235 and core 210.
When integrated circuit 200 is not being tested, testing logic 232 permits an output signal from core 210 to pass through and be placed on output pin 230. During a test, test access port control logic 240 can control testing logic 232 and thereby sample the value of the digital signal output from core 210 and normally destined to be placed on output pin 230. This captured digital value can then be sent by test access port control logic 240 out of integrated circuit 200 over the dedicated test output pin. Test access control logic 240 can also cause test logic 232 to capture a digital value sent by test access port control logic 240. Typically, this digital value is sent to integrated circuit 200 over one of the dedicated test input pins. This captured digital value can then be sent to output pin 230 from testing logic 232. In this way, test access port control logic 240 can override the output signal to be placed on output pin 230 during a test.
Referring now to bi-directional pin 250, bi-directional pin 250 can be seen to be a combination of an input pin and an output pin. Thus, an input signal placed on bi-directional pin 250 passes through testing logic 252, driver 255, and into core 210. On the other hand, an output signal from core 210 passes through driver 265, testing logic 262, and on to bi-directional pin 250. As in the case of input pin 220, when integrated circuit 200 is not being tested, testing logic 252 permits an input signal placed on bi-directional pin 250 to pass through to core 210. During a test, test access port control logic 240 can control testing logic 252 and thereby sample the value of the digital signal placed on bi-directional pin 250. This captured digital value can then be sent by test access port control logic 240 back out of integrated circuit 200 over the dedicated test output pin. Test access control logic 240 can also cause test logic 252 to capture a digital value sent by test access port control logic 240. Typically, this digital value is sent to integrated circuit 200 over one of the dedicated test input pins. This captured digital value can then be sent to core 210 from testing logic 252. In this way, test access port control logic 240 can override the input signal placed on bi-directional pin 250 during a test.
Furthermore, when integrated circuit 200 is not being tested, testing logic 262 permits an output signal from core 210 to pass through and be placed on bi-directional pin 250. During a test, test access port control logic 240 can control testing logic 262 and thereby sample the value of the digital signal output from core 210 and normally destined to be placed on bi-directional pin 250. This captured digital value can then be sent by test access port control logic 240 out of integrated circuit 200 over the dedicated test output pin. Test access control logic 240 can also cause test logic 262 to capture a digital value sent by test access port control logic 240. Typically, this digital value is sent to integrated circuit 200 over one of the dedicated test input pins. This captured digital value can then be sent to bi-directional pin 250 from testing logic 232. In this way, test access port control logic 240 can override the output signal to be placed on bi-directional pin 250 during a test.
Test access port control logic 240, test tristate control 270, testing logic blocks 222, 232, 252, and 262, along with multiplexers 237 and 267, together provide a very powerful testing tool. In a forced test mode, testing logic 222 and 252 can capture the values of respective input signals placed on input pin 220 and bi-directional pin 250. These values can then be retrieved by test access port control logic 240 and output through the signal line TEST OUT to be compared to the values placed on pins 220 and 250. By using well known test patterns (e.g. checkerboard, walking one or walking zero patterns), any open or closed defects in the connection of the input and bi-directional pins to the circuit board can be detected. Furthermore, test access port control logic 240 can use testing logic 232 and 252 to override the values of respective output signals placed on output pin 230 and bi-directional pin 250 using known values sent through the signal lines TEST IN. The signals output from pins 230 and 250 can then be compared to the known override values placed on pins 230 and 250. Once again, by using well known test patterns (e.g. checkerboard, walking one or walking zero patterns), any open or closed defects in the connection of the output and bi-directional pins to the circuit board can be detected.
Referring now to FIG. 3, a block diagram of test logic 300 is illustrated. Test logic 300 is representative of logic that is typically used when implementing a boundary scan test (i.e. testing logic 222, 232, 252 and 262 of FIG. 2). For example, in the case of test logic 222, signal NORMAL.sub.-- IN is the input signal coming from input pin 220 and signal NORMAL.sub.-- OUT is the output signal from test logic 222 to driver 225.
Test logic 300 can be used to capture the value of signal NORMAL.sub.-- IN in flip flop 310 and then provide this captured value as signal NEXT.sub.-- CELL. Test logic 300 can also be used to capture the value of signal LAST.sub.-- CELL in flip flop 310 and then force the signal NORMAL.sub.-- OUT to this value. Finally, test logic 300 can be set so that signal NORMAL.sub.-- OUT is the same as signal NORMAL.sub.-- IN.
Each of the test logic cells are linked together serially in a chain so that data can be scanned through the cells. To achieve this, the first cell in the chain receives signal LAST.sub.-- CELL from the test access port control logic and the last cell in the chain sends signal NEXT.sub.-- CELL to the test access port control logic. Every other cell in the chain receives signal LAST.sub.-- CELL from its immediately preceding cell in the chain and sends signal NEXT.sub.-- CELL to its immediately succeeding cell in the chain.
Control signals SHIFT and CLOCK are provided by the test access port control logic and control the serial scan of data. Whenever data is to be scanned, control signal SHIFT sets multiplexer 320 so that signal LAST.sub.-- CELL provides the input to flip flop 310. Signal CLOCK then controls flip flop 310 so that on each clock pulse the value stored in flip flop 310 is output from the cell as signal NEXT.sub.-- CELL and the signal LAST.sub.-- CELL is captured by flip flop 310.
In FIG. 3, control signal OVERRIDE controls multiplexer 340. During normal operation of the integrated circuit, OVERRIDE sets multiplexer 340 so that signal NORMAL.sub.-- IN input to multiplexer 340 is passed through multiplexer 340 and output as signal NORMAL.sub.-- OUT.
Control signal UPDATE is output from the test access port control logic and is a clocking signal that controls flip flop 330. The input to flip flop 330 is the output of flip flop 310. Depending upon how multiplexer 320 was set, the value stored in flip flop 310 is either the signal NORMAL.sub.-- IN or the signal LAST.sub.-- CELL. The output of flip flop 330 is provided to multiplexer 340. Thus, multiplexer 340 and flip flop 330 are used to override the value of the signal NORMAL.sub.-- IN and thereby force the value stored in flip flop 330 to appear as the signal NORMAL.sub.-- OUT.
By placing testing logic such as that of testing logic 300 in the input path between the core and each input and bi-directional pin, every input value can be sampled and retrieved, or overridden. Furthermore, by placing testing logic such as that of testing logic 300 in the output path between the core and each output and bi-directional pin, every output value can be sampled and retrieved, or overridden. Moreover, each output driver can be tristated. Although this provides a tremendous testing capability, the testing capability comes at a price. This is because mux 340 of each testing logic block provides an overhead, or delay, between core 210 and its respective pins. This overhead is in the path regardless of whether the integrated circuit is being tested or being used in its normal functionality. In a low speed system of the prior art, this delay is not particularly onerous. In a modern high speed system, however, the delay imposed by these testing logic blocks can be significant. For example, a chip that could normally run at 100 megahertz may only be able to operate at 90 megahertz when boundary scan logic is added.